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To get direct-mapped disparition, a main memory address is viewed as consisting of 3 fields. List and specify the three domains. One discipline identifies an exclusive word or perhaps byte within a block of main memory. The rest of the two areas specify one of many blocks of main memory. These two fields certainly are a line discipline, which pinpoints one of the lines of the éclipse, and a tag discipline, which pinpoints one of the obstructs that can go with that line. 3. Pertaining to set-associative refuge, a main memory space address can be considered consisting of two fields. List and specify the two areas. One discipline identifies an exceptional word or perhaps byte within block of main memory.
The two domains specify among the blocks of main memory. Both of these fields certainly are a set field, which pinpoints one of the sets of the cache, and a tag discipline, which identifies one of the obstructs that can fit into that set 4. Look at a 32-bit processor that has on-chip gigabyte four-way set-associative disparition. Assume that éclipse has a line size of several 32-bit terms. Draw a block plan of this disparition showing it is organization and exactly how the different treat fields prefer determine a cache hit/miss. Where inside the cache may be the word coming from memory location
Block frame size = 16 bytes = some doublers Quantity of block casings in cache = 18 Subtest sama dengan 1024 18 Bytes Number of sets? Quantity of block frames =1024 = 256 sets Associative Marking set Offset FACADE a few. What is the general relationship among access period, memory cost, and capability? Faster access time, higher cost every bit, greater capacity, smaller sized cost every bit, higher capacity, sluggish access time. 6. Exactly what are the differences amongst sequential access, direct access and random gain access to? Sequential get: Memory can be organized into units of data, called data.
Access has to be made in a certain linear series. Direct access: Individual blocks or perhaps records have got a unique address based on physical location. Get is achieved by direct access to succeed in the general location plus continuous searching, counting, or holding out to reach a final location. Arbitrary access: Every addressable location in memory has a exclusive, physically wired-in addressing mechanism. The time to access a given location is in addition to the sequence of prior accesses and is continuous. 7. What is the different among DRAM and SRAM in term of characteristics such as peed, size and expense?
SRAM generally have more quickly access moments than DRAMS. DRAMS are less expensive and smaller than SRAM. 8. Describe why one type of RAM is considered to be analog and also other digital. A DRAM cell is essentially a great analog system using a capacitor, the capacitor can shop any impose value within a range, a threshold value determines whether or not the charge can be interpreted while 1 or perhaps O. A SRAM cellular is a digital device, through which binary values are kept using traditional flip-flop logic-gate configurations. on the lookout for. What are differences among PROM, PROPER and flash memory?
PROM is definitely read ND written electrically, before a write operation, all the safe-keeping cells has to be erased for the same preliminary state by exposure with the packaged computer chip to ultraviolet (uv) radiation. Erasure is performed by simply shining carry on your workout ultraviolet mild through a home window that is designed in the memory computer chip. PROPER is known as a read mainly memory which can be written in to at any time devoid of erasing prior contents, only the byte or bytes dealt with are up to date. Flash storage is intermediate between PROM and APPROPRIATE in the two cost and functionality. Like PROPER, flash memory uses an electrical erasing technology.
A whole flash memory space can be erased in one or possibly a few seconds, which can be much faster than PROM. Additionally , it is possible to erase Simply blocks of memory rather than an entire nick. However , adobe flash memory will not provide byte-level erasure. Just like PROM, expensive memory uses only one transistor per little bit, and so defines the very dense (compared with PROPER) of PROM. O Design a 16-bit storage to total potential 8192 pieces using T M potato chips to size 64 little. Give the mixture configuration of the chips within the memory panel showing all requirement output and input signals for assigning this kind of memory for the lowest gown space.
The style should allow for both octet and 16-bit word access. 8192/64 = 128 potato chips, arranged in 8 series by 64 columns: 1 1 . Think about a dynamic MEMORY that must be offered a refresh cycle 64 times per ms. Every single refresh operation requires 1 nuns. What percentage of the memorys total operating time must be given to refresh? In 1 ms, the time dedicated to refresh is definitely 64 x 150 inches = 9600 ins. The fraction of time devoted to memory refresh is (9. 6th x 10-6 s)/10- since = zero. 0096, which is approximately 1%. 12. Quickly define the seven RAID levels. U: Non-redundant one particular: Mirrored, every single disk provides a mirror hard disk drive containing the same data.: Repetitive via Hamming code, a great error-correcting code is determined across corresponding bits on each of your data hard disk drive, and the bits of the code are stored in the corresponding little bit positions on multiple parity disks. 3: Bit-interleaved parity, similar to level 2 but instead of a great error-correcting code, a simple parity bit is computed to get the set of individual pieces in the same position about all of the info disks. 4: Block- interleaved parity, a bit-by-bit parity strip is calculated around corresponding whitening strips n every single data hard disk drive, and the parity bits are stored in the corresponding strip for the parity hard drive.: Block-interleaved sent out parity, comparable to level 5 but directs the parity strips across all hard disk drives. 6: Obstruct interleaved dual distributed parity, two different parity calculations are carried out and kept in separate obstructs on several disks. 13. How is redundancy achieved in a RAID system? Pertaining to RAID level 1, redundancy is attained by having two identical clones of all info. For larger levels, redundancy is attained by the use of error-correcting codes. 16. What are difficulties functions associated with an 1/0 module? Control and timing.
Processor communication. Unit communication. Info buffering. Problem detection. 12-15. List and briefly describe three tips for performing 1/0. Programmed 1/0: The cpu issues a great 1/0 control, on behalf of a procedure, to an 1/0 module, that process then busy-waits to get the procedure to be finished before continuing. Interrupt-driven 1/0: The processor issues an 1/0 command on behalf of a process, continues to do subsequent guidelines, and is cut off by the 1/0 module if the latter features completed its work.
The following instructions can be in the same process, if it is not necessary for that process to wait for the completion of the l/ To. Otherwise, the method is revoked pending the interrupt and other work is conducted. Direct memory space access (DAM): A ATTEINTE module regulates the exchange of data among main memory and an l/ m u e The processor sends a obtain tort the transfer of your block of information to the ATTEINTE module and is interrupted only after the entire block has been transferred. 18. The ATTEINTE mechanism may be configured in a variety of ways. List and explain the entire configuration.
Configuration 1: Sole Bus, Separate DAM controller Each copy uses coach twice 1/0 to DAM then DAM to memory space CPU is definitely suspended two times Configuration a couple of: Single Shuttle bus, Integrated ATTEINTE controller Control mechanism may support device Each transfer uses bus once DAM to memory CENTRAL PROCESSING UNIT is hung once Settings 3: Individual 1/0 Bus Bus facilitates all DAM enabled products 17. An immediate memory gain access to module (DAM) module is transferring characters to recollection using routine stealing, from a device sending at 9600 BSP. The processor is fetching guidelines at the charge of 1 , 000, 000 Instruction every Second (MIPS).
Consider a computer system with both segmentation and paging. When a segment is in storage, some phrases are thrown away on the last page. Additionally , for a segment size s i9000 and a website size g, there are s/p page desk entries. Small the page size, the less squander in the last webpage of the portion, but the bigger the page table. What page size minimizes the overall overhead? twenty two. What is the goal of a translation lakeside barrier? The TTL is a refuge that contains individuals page stand entries which were most recently employed. Its goal is to prevent, most of the time, having to go to disk to retrieve a webpage table admittance.
